module bit_widen #(
    parameter TIMES = 8'd2
)( 
   s_out,
   clk, rst_n, s_in
);

input  clk;
input  rst_n;
input  s_in;
output s_out;

localparam TIMES_W = 8;

reg [TIMES_W -1:0]widen_cnt;
always @(posedge clk or negedge rst_n)begin
  if(~rst_n) begin
    widen_cnt <= {TIMES_W{1'b0}};
  end
  else if(s_in && widen_cnt == {TIMES_W{1'b0}})begin
    widen_cnt <= widen_cnt + 1'b1;
  end
  else if(widen_cnt == TIMES)begin
    widen_cnt <= 1'b0;
  end
  else if(widen_cnt != {TIMES_W{1'b0}})begin
    widen_cnt <= widen_cnt + 1'b1;
  end
end

assign s_out = (widen_cnt != {TIMES_W{1'b0}});

endmodule
